In general, a semiconductor memory device uses an internal power supply voltage which is properly converted and adjusted from an external power supply voltage and applied to internal circuits.
In a semiconductor memory device which may be portioned into two regions of memory arrays and peripheral circuits, as shown in FIG. 1, each of the regions has an independent power supply voltage to be free from mutual influence of powering between the memory arrays and peripheral circuits. Therefore, the internal power supply voltages are substantially divided into one for memory arrays, one for peripheral circuits and one for data buffers, and levels of those voltages are independently established in accordance with conditions of power consumption at the regions. Internal power supply voltage generating circuit 10, as shown in FIG. 1, makes VINTA, internal power supply voltage for the memory arrays (hereinafter referred to as "array power supply voltage"), with VREFA that is reference voltage for the memory arrays (hereinafter referred to as "array reference voltage"), from external power supply voltage (hereinafter referred to as "Vcc"). Boosted voltage Vpp is generated from boosting circuit 20 which uses VINTA as a source voltage. The memory array region is formed of a plurality of cell arrays, including sense amplifiers and word line drivers (or sub word line drivers), in a SWD (sub-word-line-driver) architecture. Referring to FIG. 2 disclosing a magnified configuration of the encircled portion in FIG. 1, there are conjunction regions between the sense amplifiers and sub word line drivers. The conjunction regions, for instance, of a dynamic random access memory device, contains signal lines and power lines for operating core circuits, such as the sense amplifiers and drivers, in the cell arrays. As shown in FIG. 2, in the conjunction region, the boosted voltage Vpp is contacted into a N-well to be used as a well bias voltage therein and VINTA is connected to a P+ doped region formed in the N-well. It is well known that the Vpp is to be applied to a pair of isolation gates which is interposed between a cell array and a bit line sense amplifier consisting of P- and N-latches for the purpose of compensating a voltage drop of a data signal due to a word line voltage, and to the word line driver and a clock driver, of a DRAM or a SRAM. The applying of Vpp into the N-well is provided to reduce an influence by a latch-up effect, which can more stabilize a switching operation of a PMOS transistor which uses the N-well as a bulk region of itself.
When, like the configuration of FIG. 2, Vpp is simply applied to the N-well of bulk region of the PMOS transistor, a sectional view corresponding to FIG. 2 can be illustrated as shown in FIG. 3. VINTA generated from circuit 10 is connected to the P+ doped region (or active region) which may be a source of the PMOS transistor, and Vpp is connected to N+ doped region which is formed in the N-well, together with the P+ active region, in P-substrate. With such a connecting state, as shown in the graph of FIG. 4, since there is period Tf, within a set-up time, for which the level of Vpp is being increased, but still below that of VINTA, a forward bias path through parasitic diode D1 is inevitably formed from the P+ doped region to the N+ doped region during the period Tf, causing the latch-up phenomenon. Such an occurrence of current flowing through the forward-biased parasitic diode from VINTA to Vpp during Tf after a power-up of a memory device (i.e., the latch-up) may destroy the PMOS transistors used for pull-up transistors in a number of internal circuits, and degrades the livability and reliability of driving performance of the PMOS transistors, resulting in malfunctions of circuit operations in the memory device.
In order to overcome the aforementioned limit in obviating the latch-up, FIG. 5 shows a general example of circuit, including internal power supply voltage generating circuit 10 and one of internal circuits which is disposed with benefit of the application of latch-up protection. Circuit 10 is the type of a differential amplifier which has input terminals connected to array reference voltage VREFA and array power supply voltage VINTA, uses external power supply voltage VEXT as a source and includes a NMOS transistor which is connected to ground voltage Vss and controlled by VEXT. Array power supply voltage VINTA, as an output of the circuit 10, is applied to internal circuits 12 and 14 as power sources. Internal circuit 14 having input C and output D is connected to VINTA through NMOS transistor LNT which is provided to reduce the latch-up effect in the circuit 14, while another internal circuit 12 having input A and output B has not any means to protect itself from the latch-up effect. In circuit 14, bulk of NMOS transistor LNT is held into Vss and gate of LNT is connected to Vpp together with bulk of PMOS transistor PT1. Since the source of PMOS transistor PT1 is connected to VINTA through channel region of NMOS transistor LNT whose gate is connected to Vpp, not being connected directly to VINTA as the former case does, the forward-biased parasitic diode D1 shown in FIG. 3 can not be created therein because a voltage level at the source of PT1, appearing over NMOS transistor LNT, becomes lower than that of Vpp even in the Tf. It is possible to apply the designed configuration shown in FIG. 5 commonly to a memory device including a construction of triple well in which Vpp and VINTA are independently utilized into well bias voltages.
However, in substantial, since the NMOS transistor (e.g., LNT) for protecting the latch-up should be assigned to almost all of the internal circuit such as 14, further regions for the latch-up protection transistors are in need and thereby it is inevitable to enlarge a width for layout.